1. Field of the Invention
The present invention relates to a semiconductor memory circuit and, particularly, to a word selection circuit for activating a predetermined word line selection signal according to an address internal signal.
2. Description of the Prior Art
In a semiconductor memory circuit having a memory cell array including memory cells arranged in array, a word line selection circuit is one of circuit constructions for selecting a memory cell corresponding to an input address. The word line selection circuit receives an internal address corresponding to an address inputted externally and activates one of a plurality of word line selection signals in order to select a predetermined word line.
Generally, the word line selection circuit includes, for each word line selection signal, a decode circuit responsive to an internal address for generating a signal having a predetermined level, a drive circuit responsive to a word line activating signal for outputting a signal corresponding to an output level of the decode circuit as a word line selection signal and a precharge circuit for precharging an input point of the drive circuit to a power source voltage. Therefore, the number of such word line selection circuits corresponds to the number of word line selection signals.
With an internal signal supplied to the respective decode circuits of the word line selection circuits, an output of one of the decode circuits is maintained at high level (power source voltage level) while outputs of the remaining decode circuits are changed to low level (ground voltage level). Then, when the word line activating signal becomes high level, one of the drive circuits generates a high level, activated word line selection signal and the remaining drive circuits generate low level word line selection signals. Thus, the word line signal corresponding to the internal address is activated.
When the word line selection signal is activated in this manner, a word line corresponding thereto is driven and a memory cell connected to the word line is selected. Then, an information read out from the thus selected memory cell is amplified by a sense amplifier and a readout data is outputted.
In this case, when the sense amplifier amplifies the input information, large current flows through the ground line. As a result, a condition where a potential of the ground line rises from 0 V occurs, that is, noise is generated in the ground line.
When such noise is generated, the output levels of the decode circuits which are low are rised. Therefore, output levels of the associated drive circuits are also rised while the level of the activated word line selection signal is lowered, causing a memory cell selection to become unstable.